Substrate bias influence on the operation of junctionless nanowire transistors

dc.creatorTrevisoli R.
dc.creatorDoria R.T.
dc.creatorDe Souza M.
dc.creatorPavanello M.A.
dc.date2019-08-19T23:45:13Z
dc.date2023-05-03T20:33:12Z
dc.date2019-08-19T23:45:13Z
dc.date2023-05-03T20:33:12Z
dc.date2014
dc.date.accessioned2023-08-24T07:57:17Z
dc.date.available2023-08-24T07:57:17Z
dc.identifierTREVISOLI, Renan Doria; DORIA, Rodrigo Trevisoli; DE SOUZA, Michelly; PAVANELLO, Marcelo A.. Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors. IEEE Transactions on Electron Devices, v. 61, n. 5, p. 1575-1582, 2014.
dc.identifier0018-9383
dc.identifierhttps://hdl.handle.net/20.500.12032/88574
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8412642
dc.descriptionThe aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, the maximum transconductance, the subthreshold slope, the drain-induced barrier lowering (DIBL), and the ION/IOFF ratio are the key parameters under analysis. It has been shown that the negative back bias can reduce the short-channel effects occurrence, improving the ION/ OFF ratio and DIBL. © 1963-2012 IEEE.
dc.relationIEEE Transactions on Electron Devices
dc.rightsAcesso Restrito
dc.titleSubstrate bias influence on the operation of junctionless nanowire transistors
dc.typeArtigo


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