Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

dc.creatorBenfica J.
dc.creatorGreen B.
dc.creatorPorcher B.C.
dc.creatorPoehls L.B.
dc.creatorVargas F.
dc.creatorMedina N.H.
dc.creatorAdded N.
dc.creatorDe Aguiar V.A.P.
dc.creatorMacchione E.L.A.
dc.creatorAguirre F.
dc.creatorSilveira M.A.G.
dc.creatorPerez M.
dc.creatorSofo Haro M.
dc.creatorSidelnik I.
dc.creatorBlostein J.
dc.creatorLipovetzky J.
dc.creatorBezerra E.A.
dc.date2019-08-19T23:47:19Z
dc.date2023-05-03T20:39:03Z
dc.date2019-08-19T23:47:19Z
dc.date2023-05-03T20:39:03Z
dc.date2016
dc.date.accessioned2023-08-24T04:29:55Z
dc.date.available2023-08-24T04:29:55Z
dc.identifierVARGAS, FABIAN; BENFICA, J.; POEHLS, L. B.; HARO, M. S.; SILVEIRA, M. A. G.; MEDINA, N. H.; ADDED, N.; V. A. P. Aguiar; BEZERRA, E. A.; LIPOVETZKY, J.; BLOSTEIN, J.; SIDELNIK, I.. Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects. IEEE Transactions on Nuclear Science, v. 63, p. 1294-1300, 2016.
dc.identifier0018-9499
dc.identifierhttps://hdl.handle.net/20.500.12032/89696
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8406122
dc.description© 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241 AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.
dc.relationIEEE Transactions on Nuclear Science
dc.rightsAcesso Restrito
dc.titleAnalysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects
dc.typeArtigo


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