Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

dc.creatorGALEMBECK, EGON H.S.
dc.creatorRENAUX, CHRISTIAN
dc.creatorFLANDRE, Denis
dc.creatorFINCO, SAULO
dc.creatorGIMENEZ, SALVADOR P.
dc.date.accessioned2019-08-19T23:45:29Z
dc.date.accessioned2023-05-03T20:33:14Z
dc.date.accessioned2023-08-23T23:02:10Z
dc.date.available2019-08-19T23:45:29Z
dc.date.available2023-05-03T20:33:14Z
dc.date.available2023-08-23T23:02:10Z
dc.date.created2019-08-19T23:45:29Z
dc.date.created2023-05-03T20:33:14Z
dc.date.issued2017
dc.identifierGALEMBECK, EGON H.S.; RENAUX, CHRISTIAN; FLANDRE, Denis; FINCO, SAULO; GIMENEZ, SALVADOR P.. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v. 17, n. 1, p. 1-1, 2017.
dc.identifier1530-4388
dc.identifierhttps://hdl.handle.net/20.500.12032/88581
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8395037
dc.relationIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
dc.rightsAcesso Aberto
dc.titleBoosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
dc.typeArtigo


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