High-Frequency Electronic Design Optimization Using Simulated Annealing

dc.creatorAlejos-Jiménez, Jesús R.
dc.date.accessioned2017-11-30T20:24:23Z
dc.date.accessioned2023-03-21T17:12:41Z
dc.date.accessioned2023-08-23T22:07:18Z
dc.date.available2017-11-30T20:24:23Z
dc.date.available2023-03-21T17:12:41Z
dc.date.available2023-08-23T22:07:18Z
dc.date.created2017-11-30T20:24:23Z
dc.date.created2023-03-21T17:12:41Z
dc.date.issued2017-11
dc.identifierAlejos-Jiménez, J. R. (2017). High-Frequency Electronic Design Optimization Using Simulated Annealing. Trabajo de obtención de grado, Maestría en Diseño Electrónico. Tlaquepaque, Jalisco: ITESO.
dc.identifierhttps://hdl.handle.net/20.500.12032/74066
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8390964
dc.languageeng
dc.publisherITESO
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf
dc.subjectHigh-frequency Electronic Design
dc.subjectSimulated Annealing
dc.subjectOptimization
dc.titleHigh-Frequency Electronic Design Optimization Using Simulated Annealing
dc.typeinfo:eu-repo/semantics/masterThesis


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