A novel voltage-mode CMOS quaternary logic design

dc.creatorSilva, Ricardo Cunha Gonçalves da
dc.creatorBoudinov, Henri Ivanov
dc.creatorCarro, Luigi
dc.date2011-01-28T05:59:11Z
dc.date2006
dc.identifier0018-9383
dc.identifierhttp://hdl.handle.net/10183/27584
dc.identifier000565276
dc.descriptionThis brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.
dc.formatapplication/pdf
dc.languageeng
dc.relationIEEE transactions on electron devices. New York. Vol. 53, n. 6 (June 2006), p. 1480-1483
dc.rightsOpen Access
dc.subjectInverter
dc.subjectMultiple-valued logic (MVL) circuits
dc.subjectNMAX
dc.subjectNMIN
dc.subjectVoltage-mode quaternary
dc.subjectCMOS desig
dc.subjectMicroeletrônica
dc.titleA novel voltage-mode CMOS quaternary logic design
dc.typeArtigo de periódico
dc.typeEstrangeiro


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