A compact model of MOSFET mismatch for circuit design

dc.creatorMontoro, Carlos Galup
dc.creatorSchneider, Marcio Cherem
dc.creatorKlimach, Hamilton Duarte
dc.creatorArnaud, Alfredo
dc.date2011-01-28T05:59:10Z
dc.date2005
dc.identifier0018-9200
dc.identifierhttp://hdl.handle.net/10183/27580
dc.identifier000510147
dc.descriptionThis paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 m technology confirm the accuracy of our mismatch model under various bias conditions.
dc.formatapplication/pdf
dc.languageeng
dc.relationIEEE journal of solid-state circuits. New York, N. Y. vol. 40, no. 8 (Aug. 2005), p. 1649-1657
dc.rightsOpen Access
dc.subjectMOSFET
dc.subjectAnalog design
dc.subjectMatching
dc.subjectMismatch
dc.subjectCompact models
dc.subjectCircuitos eletrônicos
dc.subjectMicroeletrônica
dc.titleA compact model of MOSFET mismatch for circuit design
dc.typeArtigo de periódico
dc.typeEstrangeiro


Este ítem pertenece a la siguiente institución