dc.creatorBampi, Sergio
dc.creatorPlummer, James D.
dc.date2011-01-28T05:59:01Z
dc.date1986
dc.identifier0018-9383
dc.identifierhttp://hdl.handle.net/10183/27552
dc.identifier000059152
dc.descriptionA new n-MOS LDD-like device structure (the J-MOS transistor) is proposed. It’s design, simulation, and fabrication are studied in this paper. n-channel MOSFET’s with Le, below 2µm suffer from high-field effects that must be overcome to secure reliable 5-V operation. LDD structures alleviate these effects, but their reliability is better than that of conventional MOSFET’s only if the n¯ regions have a peak doping density above 1 X 10 18 cm¯3. To overcome this limitation and to allow constant voltage scaling for devices into the submicrometer regime, the J-MOS structure uses a series drain JFET to drop part of the supply voltage. Both 2-D device simulations and experimental results are presented to demonstrate the operation of this device and its potential for applications requiring reliable submicrometer device operation under maximum supply voltage.(Continue0 The major experimental findings are that the J-MOS structure can sustain 5-V operation even for submicrometer effective channel lengths. As has been the case with all LDD-like structures, improved device reliability has been achieved at the expense of some performance. However, the advantages of keeping 5-V operation in micrometer-sized devices may outweigh this performance loss.
dc.formatapplication/pdf
dc.languageeng
dc.relationIEEE Transactions on Electron Devices. New York. vol. ed-33, n. 11 (nov. 1986), p. 1769-1779
dc.rightsOpen Access
dc.subjectMicroeletrônica
dc.titleA modified lightly doped drain structure for vlsi mosfet's
dc.typeArtigo de periódico
dc.typeEstrangeiro


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