Simulación de un esquema de un esquema de fec (forward error correction) en base al estandar dvb (digital video broadcasting)

dc.creatorMoscoso Alvarado, Jaime Armando
dc.creatorMedina Moreira, Washington Adolfo
dc.date2009-04-21
dc.date2009-04-21
dc.date2009-04-21
dc.date.accessioned2023-08-08T22:15:29Z
dc.date.available2023-08-08T22:15:29Z
dc.identifierhttp://www.dspace.espol.edu.ec/handle/123456789/4857
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8088545
dc.descriptionThe wireless communication medium requires employing forward error correction methods on the data transferred, where Reed-Solomon & Viterbi coding techniques are generally utilized, because of performance and security reason. In this paper we present a modular design of phase encoding these codes for concatenation using System Generator of Xilinx and oriented to implementation with field programmable gate arrays (FPGA). The work begins with a review of code concept and the definition of the components and the model and the description of the behavioral. Later, the architecture is made based in model based design. The scheme of FEC will be done according to the specifications of the DVB standard for the digital Digital television.
dc.formatapplication/pdf
dc.languagespa
dc.rightsopenAccess
dc.subjectCODIFICADOR
dc.subjectDECODIFICADOR
dc.subjectREED-SOLOMON
dc.subjectVITERBI
dc.subjectPUNCTURING
dc.subjectINTERLEAVING
dc.titleSimulación de un esquema de un esquema de fec (forward error correction) en base al estandar dvb (digital video broadcasting)
dc.typeArticle


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