dc.creatorEduardo Cuevas Farfán
dc.creatorMIGUEL MORALES SANDOVAL
dc.creatorALICIA MORALES REYES
dc.creatorCLAUDIA FEREGRINO URIBE
dc.creatorIgnacio Algredo Badillo
dc.creatorParis Kitsos
dc.creatorRENE ARMANDO CUMPLIDO PARRA
dc.date2013
dc.date.accessioned2023-07-25T16:25:31Z
dc.date.available2023-07-25T16:25:31Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2396
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807572
dc.descriptionIn this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.
dc.formatapplication/pdf
dc.languageeng
dc.publisherAdvances in Electrical and Computer Engineering
dc.relationcitation:Cuevas, E., et al., (2013). Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m), Advances in Electrical and Computer Engineering, Vol. 13 (2): 3-10
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Data security/Data security
dc.subjectinfo:eu-repo/classification/Cryptography/Cryptography
dc.subjectinfo:eu-repo/classification/Public key/Public key
dc.subjectinfo:eu-repo/classification/Algorithm design and analysis/Algorithm design and analysis
dc.subjectinfo:eu-repo/classification/Field programmable gate arrays/Field programmable gate arrays
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/12
dc.subjectinfo:eu-repo/classification/cti/1203
dc.subjectinfo:eu-repo/classification/cti/1203
dc.titleKaratsuba-Ofman Multiplier with Integrated Modular Reduction for (2m )
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceteachers
dc.audiencegeneralPublic


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