Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

dc.creatorIvick Guerra Gomez
dc.creatorESTEBAN TLELO CUAUTLE
dc.date2013
dc.date.accessioned2023-07-25T16:25:29Z
dc.date.available2023-07-25T16:25:29Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2381
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807557
dc.descriptionThis work shows the usefulness of assigning current-branches-bias levels, in order to improve and accelerate the sizing optimization of MOSFET-based analog integrated circuits (ICs). That way, the proposed procedure relies on the search of current branches from the associated incidence matrix by applying a recursive technique for exploring circuit graphs. The goal is focused on determining the bounds of the width/length (W/L) search space for each MOSFET before starting the sizing optimization process. As a case of study, the proposed current-branches-bias assignment (CBBA) approach is applied in the sizing optimization of the recycled folded cascode operational transconductance amplifier by applying evolutionary algorithms (EAs). From the feasible optimization results, we conclude that our proposed CBBA approach enhances and accelerates the biasing and sizing of analog ICs by EAs.
dc.formatapplication/pdf
dc.languageeng
dc.publisherElektronika ir elektrotechnika
dc.relationcitation:Guerra-Gomez, I., and Tlelo-Cuautle, E., (2013), Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics, Elektronika ir elektrotechnika, Vol. 19(10):81-86
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Inspec/MOSFET
dc.subjectinfo:eu-repo/classification/Inspec/Operational transconductance amplifier
dc.subjectinfo:eu-repo/classification/Inspec/Incidence matrix
dc.subjectinfo:eu-repo/classification/Inspec/Topological circuit analysis
dc.subjectinfo:eu-repo/classification/Inspec/Biasing
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleSizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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