FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256

dc.creatorIgnacio Algredo Badillo
dc.creatorCLAUDIA FEREGRINO URIBE
dc.creatorRENE ARMANDO CUMPLIDO PARRA
dc.creatorMIGUEL MORALES SANDOVAL
dc.date2013
dc.date.accessioned2023-07-25T16:25:25Z
dc.date.available2023-07-25T16:25:25Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2343
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807519
dc.descriptionHash function algorithms are widely used to provide security services of integrity and authentication, being SHA-2 the latest set of hash algorithms standardized by the US Federal Government. The main com- putation block in SHA-2 algorithms is governed by a loop with high data dependence for which several implementation strategies are explored in this work as well as designs efficiently mapped to hardware architectures. Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows. The pro- posed designs were implemented and validated in the FPGA Virtex-2 XC2VP-7. The achieved results show a significant improvement on the performance of the SHA-256 algorithm compared to similar previously proposed approaches, obtaining a throughput of 909 Mbps and an improved efficiency of 0.713 Mbps/ slice.
dc.formatapplication/pdf
dc.languageeng
dc.publisherElsevier B.V.
dc.relationcitation:Badillo, I.A., et al., (2013). FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256, Microprocessors and Microsystems, Vol. (37): 750–757
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/SHA-2/SHA-2
dc.subjectinfo:eu-repo/classification/Hash function/Hash function
dc.subjectinfo:eu-repo/classification/FPGA/FPGA
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/12
dc.subjectinfo:eu-repo/classification/cti/1203
dc.subjectinfo:eu-repo/classification/cti/1203
dc.titleFPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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