Experimental performance analysis of a CMOS amplifier considering different layout techniques

dc.creatorCARLOS ZUÑIGA ISLAS
dc.creatorMONICO LINARES ARANDA
dc.date2013-10-25
dc.date.accessioned2023-07-25T16:25:22Z
dc.date.available2023-07-25T16:25:22Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2315
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807494
dc.descriptionIn order to obtain high-performance systems on chip (SoC) using complementary metal oxide semiconductor (CMOS) technology is necessary to increase the robustness and decrease the delay, power consumption, and surface area of the integrated circuits. We present an experimental performance analysis of a class AB CMOS amplifier designed with different layout techniques (serpentine, concentric, and interdigitated). These layout techniques are evaluated in function of product potency delay area and amplifier characteristics such as electrical gain, common mode rejection ratio, power supply rejection ratio, offset, and slew rate. Based on the experimental performance results of the class AB CMOS amplifier, serpentine technique reduces its surface area to 64 %, and decreases the power consumption close to 39 % with respect to the conventional technique. In the SoC design, serpentine layout technique could be used to improve the electrical performance of their CMOS amplifiers.
dc.formatapplication/pdf
dc.languageeng
dc.publisherAnalog Integrated Circuits and Signal Processing
dc.relationcitation:López-Huerta, F., et al., (2013), Experimental performance analysis of a CMOS amplifier considering different layout techniques, Analog Integrated Circuits and Signal Processing, Vol. 78(3): 799–806
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Inspec/CMOS amplifier
dc.subjectinfo:eu-repo/classification/Inspec/Integrated circuits
dc.subjectinfo:eu-repo/classification/Inspec/Layout techniques
dc.subjectinfo:eu-repo/classification/Inspec/Systems on chip
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleExperimental performance analysis of a CMOS amplifier considering different layout techniques
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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