| dc.creator | Héctor Luis Villacorta Minaya | |
| dc.creator | Víctor Hugo Champac Vilela | |
| dc.date | 2013-09-09 | |
| dc.date.accessioned | 2023-07-25T16:25:18Z | |
| dc.date.available | 2023-07-25T16:25:18Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2282 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7807461 | |
| dc.description | Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening. One is related to increasing the number of fins of the transistors composing the cross-coupled inverters. This option provides a significant increase of the cell critical charge (Qcrit), but with a cost in area. The other alternative increases the transistors fin height. Results show that a similar Qcrit gain is achieved by increasing the fin height instead of the number of fins without area overhead. The impact of process variations has been considered. Qcrit distribution has been modeled through an statistical approach based on Design of Experiments. Results are presented for a 10nm-SOI Trigate FinFET technology. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS) | |
| dc.relation | citation:Villacorta, Hector, et al., (2013), FinFET SRAM hardening through design and technology parameters considering process variations, Proc. RADECS 2013 C-1:1-7 | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Inspec/CMOS memory circuits | |
| dc.subject | info:eu-repo/classification/Inspec/Integrated circuit design | |
| dc.subject | info:eu-repo/classification/Inspec/Integrated circuit reliability | |
| dc.subject | info:eu-repo/classification/Inspec/Logic gates | |
| dc.subject | info:eu-repo/classification/Inspec/Radiation hardening (electronics) | |
| dc.subject | info:eu-repo/classification/Inspec/Silicon-on-insulator | |
| dc.subject | info:eu-repo/classification/Inspec/SRAM chips | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.title | FinFET SRAM hardening through design and technology parameters considering process variations | |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
