| dc.creator | JOSE ROBERTO PEREZ ANDRADE | |
| dc.creator | CESAR TORRES HUITZIL | |
| dc.creator | RENE ARMANDO CUMPLIDO PARRA | |
| dc.date | 2013 | |
| dc.date.accessioned | 2023-07-25T16:25:18Z | |
| dc.date.available | 2023-07-25T16:25:18Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2276 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7807456 | |
| dc.description | The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Electronics Express | |
| dc.relation | citation:Perez-Andrade, R., et al., (2013). On an external memory scheme for processor arrays, Vol. 10 (14): 1-12 | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Prosessor arrays/Prosessor arrays | |
| dc.subject | info:eu-repo/classification/Loop-based Algorithms/Loop-based Algorithms | |
| dc.subject | info:eu-repo/classification/External Memory Interface/External Memory Interface | |
| dc.subject | info:eu-repo/classification/FPGA/FPGA | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/12 | |
| dc.subject | info:eu-repo/classification/cti/1203 | |
| dc.subject | info:eu-repo/classification/cti/1203 | |
| dc.title | On an external memory scheme for processor arrays | |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
