Study and comparison of CMOS layouts for applications in analog circuits

dc.creatorMONICO LINARES ARANDA
dc.creatorCARLOS ZUÑIGA ISLAS
dc.date2012-04
dc.date.accessioned2023-07-25T16:25:00Z
dc.date.available2023-07-25T16:25:00Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2124
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807305
dc.descriptionThis study presents different layouts techniques (serpentine, concentric, interdigitated) applied to a differential amplifier designed in commercial technology CMOS (0.6 μm). It was observed that serpentine technique improves by 6 to 7 electrical parameters, where area was reduced (64%) and power consumption diminishes until a 57% with respect to conventional technique. Thus designer can optimally use different abstraction levels during integrated circuits (IC) design, by applying the best layout technique towards efficient systems.
dc.formatapplication/pdf
dc.languageeng
dc.publisherJournal of Scientific and Industrial Research
dc.relationcitation:López, Francisco, et al., (2012), Study and comparison of CMOS layouts for applications in analog circuits, Journal of Scientific and Industrial Research, Vol. 71(4):257–261
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Inspec/Integrated circuit (IC)
dc.subjectinfo:eu-repo/classification/Inspec/Layout
dc.subjectinfo:eu-repo/classification/Inspec/Operational amplifier
dc.subjectinfo:eu-repo/classification/Inspec/Serpentine
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleStudy and comparison of CMOS layouts for applications in analog circuits
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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