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Performance improvement of low-temperature a-SiGe:H thin-film transistors

dc.creatorMiguel Dominguez
dc.creatorPedro Rosales Quintero
dc.creatorALFONSO TORRES JACOME
dc.date2012
dc.date.accessioned2023-07-25T16:24:58Z
dc.date.available2023-07-25T16:24:58Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2104
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807285
dc.descriptionThis paper presents the study of an interface preparation procedure in the source/drain regions of the active layer, prior to deposit the n+ a-Ge:H contact layer in the fabrication process of low-temperature a-SiGe:H thin-film transistors. The devices were fabricated on corning 1737 substrates at 200 °C. The improvement in metal–semiconductor interface by the interface preparation procedure was demonstrated. This interface improvement translates in higher mobility and better values of off-current, on/off-current ratio, subthreshold slope and threshold voltage.
dc.formatapplication/pdf
dc.languageeng
dc.publisherSolid-State Electronics
dc.relationcitation:Dominguez, Miguel, et al., (2012), Performance improvement of low-temperature a-SiGe:H thin-film transistors, Solid-State Electronics, Vol. 76:44–47
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Inspec/Thin-film transistor
dc.subjectinfo:eu-repo/classification/Inspec/Hydrogenated amorphous silicon–germanium
dc.subjectinfo:eu-repo/classification/Inspec/Hydrogen plasma
dc.subjectinfo:eu-repo/classification/Inspec/Low-temperature
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titlePerformance improvement of low-temperature a-SiGe:H thin-film transistors
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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