A design-oriented methodology for accurate modeling of on-chip Interconnects

dc.creatorOSCAR GONZÁLEZ DÍAZ
dc.creatorMONICO LINARES ARANDA
dc.creatorReydezel Torres Torres
dc.date2012
dc.date.accessioned2023-07-25T16:24:56Z
dc.date.available2023-07-25T16:24:56Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2093
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807274
dc.descriptionAn accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.
dc.formatapplication/pdf
dc.languageeng
dc.publisherAnalog Integr. Circ. Sig. Process
dc.relationcitation:Gonzalez-Diaz, Oscar, et al., (2012), A design-oriented methodology for accurate modeling of on-chip interconnects, Analog Integr. Circ. Sig. Process, Vol. 71:221–230
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Inspec/ABCD matrix
dc.subjectinfo:eu-repo/classification/Inspec/De-embedding procedure
dc.subjectinfo:eu-repo/classification/Inspec/Interconnection lines
dc.subjectinfo:eu-repo/classification/Inspec/Lumped equivalent circuit
dc.subjectinfo:eu-repo/classification/Inspec/Distributed equivalent circuit
dc.subjectinfo:eu-repo/classification/Inspec/Modeling
dc.subjectinfo:eu-repo/classification/Inspec/S-parameters
dc.subjectinfo:eu-repo/classification/Inspec/VLSI circuits
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleA design-oriented methodology for accurate modeling of on-chip Interconnects
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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