Testing of Stuck-Open Faults in Nanometer Technologies

dc.creatorVíctor Hugo Champac Vilela
dc.creatorJULIO CESAR VAZQUEZ HERNANDEZ
dc.date2012-08
dc.date.accessioned2023-07-25T16:24:52Z
dc.date.available2023-07-25T16:24:52Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2059
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807241
dc.descriptionFailure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests. VDimitris Gizopoulos, University of Athens
dc.formatapplication/pdf
dc.languageeng
dc.publisherIEEE Design & Test of Computers
dc.relationcitation:Champac, V., et al., (2012), Testing of Stuck-Open Faults in Nanometer Technologies, IEEE Design & Test of Computers, Vol. 29(4): 80–91.
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Inspec/Failure analysis
dc.subjectinfo:eu-repo/classification/Inspec/Fault diagnosis
dc.subjectinfo:eu-repo/classification/Inspec/Integrated circuit reliability
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleTesting of Stuck-Open Faults in Nanometer Technologies
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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