dc.creatorFernando Martín del Campo Ramírez
dc.creatorALICIA MORALES REYES
dc.creatorJOSE ROBERTO PEREZ ANDRADE
dc.creatorRENE ARMANDO CUMPLIDO PARRA
dc.creatorALDO GUSTAVO OROZCO LUGO
dc.creatorCLAUDIA FEREGRINO URIBE
dc.date2012
dc.date.accessioned2023-07-25T16:24:33Z
dc.date.available2023-07-25T16:24:33Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1899
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7807090
dc.descriptionThis paper presents a module that solves the square root by obtaining a number of more significant bits from a look-up table as an approximate root. A set of possible roots are then appended and squared for comparison to the original radicand, finely tuning the calculation. The module stops as soon as it finds an exact root, therefore not all entries take the same number of cycles, reducing the number of iterations required for full resolution. The proposed FPGA module overcomes a Xilinx’s logiCORE IP in terms of resources utilization and in several cases latency due to its flexible structure configuration.
dc.formatapplication/pdf
dc.languageeng
dc.publisherIEICE Electronics Express
dc.relationcitation:Martin del Campo, F., et al., (2012). A multi-cycle fixed point square root module for FPGAs, IEICE Electronics Express, Vol. 9 (11): 971-977
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Square root/Square root
dc.subjectinfo:eu-repo/classification/Non-restoring algorithm/Non-restoring algorithm
dc.subjectinfo:eu-repo/classification/FPGA/FPGA
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/12
dc.subjectinfo:eu-repo/classification/cti/1203
dc.subjectinfo:eu-repo/classification/cti/1203
dc.titleA multi-cycle fixed point square root module for FPGAs
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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