Noise margin and short-circuit current in FGMOS logics

dc.creatorLuis Fortino Cisneros Sinencio
dc.creatorALEJANDRO DIAZ SANCHEZ
dc.creatorJaime Ramírez Angulo
dc.date2011
dc.date.accessioned2023-07-25T16:24:13Z
dc.date.available2023-07-25T16:24:13Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1726
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7806918
dc.descriptionEven when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.
dc.formatapplication/pdf
dc.languageeng
dc.publisherIEICE Electronics Express
dc.relationcitation:Cisneros-Sinencio, L.F., et al., (2011). Noise margin and short-circuit current in FGMOS logics, IEICE Electronics Express, Vol. 8 (23): 1967-1971
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Floating-gate logic/Floating-gate logic
dc.subjectinfo:eu-repo/classification/Noise margin/Noise margin
dc.subjectinfo:eu-repo/classification/FGMOS transistor/FGMOS transistor
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleNoise margin and short-circuit current in FGMOS logics
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceteachers
dc.audiencegeneralPublic


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