| dc.creator | JOSE JUAN GARCIA HERNANDEZ | |
| dc.creator | CLAUDIA FEREGRINO URIBE | |
| dc.creator | RENE ARMANDO CUMPLIDO PARRA | |
| dc.creator | CAROLINA RETA CASTRO | |
| dc.date | 2011 | |
| dc.date.accessioned | 2023-07-25T16:23:58Z | |
| dc.date.available | 2023-07-25T16:23:58Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1595 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7806790 | |
| dc.description | Data hiding systems have emerged as a solution against the piracy problem, particularly those based on quantization have been widely used for its simplicity and high performance. Several data hiding applications, such as broadcasting monitoring and live performance watermarking, require a real-time multi-channel behavior. While Digital Signal Processors (DSP) have been used for implementing these schemes achieving real-time performance for audio signal processing, custom hardware architectures offer the possibility of fully exploiting the inherent parallelism of this type of algorithms for more demanding applications. This paper presents an efficient hardware implementation of a Rational Dither Modulation (RDM) algorithm-based data hiding system in the Modulated Complex Lapped Transform (MCLT) domain. In general terms, the proposed hardware architecture is conformed by an MCLT processor, an Inverse MCLT processor, a Coordinate Rotation Digital Computer (CORDIC) and an RDM-QIM processor. Results of implementing the proposed hardware architecture a Field Programmable Gate Array (FPGA) are presented and discussed. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Springer Science+Business Media | |
| dc.relation | citation:Garcia-Hernandez, J.J., et al., (2011). On the implementation of a hardware architecture for an audio data hiding system, Journal of Signal Processing Systems (64): 457–468 | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Data hiding/Data hiding | |
| dc.subject | info:eu-repo/classification/Audio signal/Audio signal | |
| dc.subject | info:eu-repo/classification/FPGA/FPGA | |
| dc.subject | info:eu-repo/classification/Multi-channel processing/Multi-channel processing | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/12 | |
| dc.subject | info:eu-repo/classification/cti/1203 | |
| dc.subject | info:eu-repo/classification/cti/1203 | |
| dc.title | On the implementation of a hardware architecture for an audio data hiding system | |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
