A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter

dc.creatorJOSE ROBERTO PEREZ ANDRADE
dc.creatorRENE ARMANDO CUMPLIDO PARRA
dc.creatorCLAUDIA FEREGRINO URIBE
dc.creatorFERNANDO MARTIN DEL CAMPO RAMIREZ
dc.date2010
dc.date.accessioned2023-07-25T16:23:34Z
dc.date.available2023-07-25T16:23:34Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1397
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7806593
dc.descriptionConstant False Alarm Rate (CFAR) algorithms are used in digital signal processing applications to extract targets from background in noisy environments. Some examples of applications are target detection in radar environments, image processing, medical engineering, power quality analysis, features detection in satellite images, Pseudo-Noise (PN) code detectors, among others. This paper presents a versatile hardware architecture that implements six variants of the CFAR algorithm based on linear and nonlinear operations for radar applications. Since some implemented CFAR algorithms require sorting the input samples, a linear sorter based on a First In First Out (FIFO) schema is used. The proposed architecture, known as CFAR processor, can be used as a specialized module or co-processor for Software Defined Radar (SDR) applications. The results of implementing the CFAR processor on a Field Programmable Gate Array (FPGA) are presented and discussed.
dc.formatapplication/pdf
dc.languageeng
dc.publisherElsevier Inc.
dc.relationcitation:Perez-Andrade, R., et al., (2010). A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter, Digital Signal Processing, (20): 1733–1747
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/CFAR processor/CFAR processor
dc.subjectinfo:eu-repo/classification/Software defined radar/Software defined radar
dc.subjectinfo:eu-repo/classification/Hardware architecture/Hardware architecture
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/12
dc.subjectinfo:eu-repo/classification/cti/1203
dc.subjectinfo:eu-repo/classification/cti/1203
dc.titleA versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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