| dc.creator | JESUS EZEQUIEL MOLINAR SOLIS | |
| dc.creator | RODOLFO ZOLA GARCIA LOZANO | |
| dc.creator | IVAN RODRIGO PADILLA CANTOYA | |
| dc.creator | ALEJANDRO DIAZ SANCHEZ | |
| dc.creator | JOSE MIGUEL ROCHA PEREZ | |
| dc.date | 2009 | |
| dc.date.accessioned | 2023-07-25T16:23:15Z | |
| dc.date.available | 2023-07-25T16:23:15Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1229 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7806426 | |
| dc.description | In this work, an experimental comparison between measured FG CMOS inverters using the quasifloating gate (QFG) and layout-based (L-b) techniques for charge removal in the Floating-gate (FG) and simulations through PSpice is presented. The experiment was developed through the measurements of 40 different IC’s with a total of 200 FG and QFG CMOS inverters characterized on AMI C5FN 0.5 lm technology. The data obtained shows that the layout-based technique reduces the initial charge present at the FG, but presents a very small residual charge. Nevertheless, the offset associated to the charge follows a normal distribution and is predictable. Comparison between measured QFG inverters and simulations shows that the high resistance parasitic diode must be modeled accurately for a proper simulation. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Springer Science+Business Media | |
| dc.relation | citation:Molinar-Solis, J.E., et al., (2009). On the characterization of the trapped charge in FG-CMOS inverters, Analog Integr Circ Sig Process (61): 191–198 | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Neuron-MOS/Neuron-MOS | |
| dc.subject | info:eu-repo/classification/vMOS/vMOS | |
| dc.subject | info:eu-repo/classification/Floating-gate transistors/Floating-gate transistors | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.title | On the characterization of the trapped charge in FG-CMOS inverters | |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
