On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm

dc.creatorTOMAS BALDERAS CONTRERAS
dc.creatorRENE ARMANDO CUMPLIDO PARRA
dc.creatorCLAUDIA FEREGRINO URIBE
dc.date2008
dc.date.accessioned2023-07-25T16:22:47Z
dc.date.available2023-07-25T16:22:47Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/995
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7806194
dc.descriptionModern cellular networks allow users to transmit information at high data rates, have access to IP-based networks deployed around the world, and access to sophisticated services. In this context, not only is it necessary to develop new radio interface technologies and improve existing core networks to reach success, but guaranteeing confidentiality and integrity during transmission is a must. The KASUMI block cipher lies at the core of both the f8 data confidentiality algorithm and the f9 data integrity algorithm for Universal Mobile Telecommunications System networks. KASUMI implementations must reach high performance and have low power consumption in order to be adequate for network components. This paper describes a specialized processor core designed to efficiently perform the KASUMI algorithm. Experimental results show two orders of magnitude performance improvement over software only based implementations. We describe the used design technique that can also be applied to implement other Feistel-like ciphering algorithms. The proposed architecture was implemented on a FPGA, results are presented and discussed.
dc.formatapplication/pdf
dc.languageeng
dc.publisherElsevier Ltd
dc.publisherScience Direct
dc.relationcitation:Balderas-Contreras, T., et al., (2008). On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm, Computers and Electrical Engineering (34): 531–546
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Cryptography/Cryptography
dc.subjectinfo:eu-repo/classification/Block cipher/Block cipher
dc.subjectinfo:eu-repo/classification/KASUMI/KASUMI
dc.subjectinfo:eu-repo/classification/Hardware implementation/Hardware implementation
dc.subjectinfo:eu-repo/classification/RISC Processors/RISC Processors
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/12
dc.subjectinfo:eu-repo/classification/cti/1203
dc.subjectinfo:eu-repo/classification/cti/1203
dc.titleOn the design and implementation of a RISC processor extension for the KASUMI encryption algorithm
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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