| dc.creator | ANTONIO ZENTENO RAMIREZ | |
| dc.creator | GUILLERMO ESPINOSA FLORES VERDAD | |
| dc.creator | VICTOR HUGO CHAMPAC VILELA | |
| dc.date | 2007-05 | |
| dc.date.accessioned | 2023-07-25T16:22:35Z | |
| dc.date.available | 2023-07-25T16:22:35Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/895 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7806095 | |
| dc.description | In this paper, a design-for-testability (DFT) technique
to test open defects in otherwise undetectable faulty branches in
fully static CMOS latches and flip-flops is proposed. The main benefits
of our proposal are: 1) it is able to detect a parametric range of
resistive opens defects and 2) the performance degradation is very
low. The testability of the added DFT circuitry is also addressed.
The cost of the proposed technique in terms of speed degradation,
area overhead, and extra pins is analyzed. Comparison with other
previously proposed testable latches is carried out. Circuits with
the proposed technique have been designed and fabricated. Good
agreement is observed between the analytical analysis, simulations
and experimental measures performed on the fabricated circuits. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | |
| dc.relation | citation:Antonio Zenteno Ramirez | |
| dc.relation | citation:Guillermo Espinosa | |
| dc.relation | citation:Victor Champac | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/DFT/Design-for-testability | |
| dc.subject | info:eu-repo/classification/Flip-flops/Flip-flops | |
| dc.subject | info:eu-repo/classification/Latches/Latches | |
| dc.subject | info:eu-repo/classification/Resistive opens/Resistive opens | |
| dc.subject | info:eu-repo/classification/Undetected opens/Undetected opens | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.title | Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops | |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
