| dc.contributor | ESTEBAN TLELO CUAUTLE | |
| dc.creator | ADRIANA CAROLINA SANABRIA BORBON | |
| dc.date | 2014-08 | |
| dc.date.accessioned | 2023-07-25T16:21:07Z | |
| dc.date.available | 2023-07-25T16:21:07Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/206 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7805427 | |
| dc.description | Automatic biasing and sizing of analog integrated circuits (ICs) remains an open challenge.
This Thesis introduces an automatic technique for sizing analog ICs through
combining multi-objective optimization techniques and the gm/ID design technique. In
this manner, two evolutionary algorithms are described and they are applied as monoand
multi-objective algorithms for optimizing analog ICs. They are known as: differential
evolution (DE) and non-dominated sorting genetic algorithm (NSGA-II), respectively.
Although current literature summarizes recent sizing techniques for analog ICs, those
techniques do not consider the usefulness of exploiting the advantages of biasing techniques,
which can enhance DE and NSGA-II algorithms to guarantee DC operating
conditions of transistors, and to limit the search space of evolutionary algorithms. That
way, this Thesis highlights the advantages of using the gm/ID design technique for establishing
the sizes, width (W) and length (L) ranges, for each transistor while guaranteeing
the appropriate bias levels conditions. The established feasible sizes ranges become the
initial search spaces for Ws/Ls when performing automatic IC optimization.
The experiments shown herein, lets us concluding on the appropriateness of applying the
gm/ID design technique to accelerate the computation time of evolutionary algorithms
for optimizing analog ICs. This Thesis discusses the main advantages of this biasing and
sizing approach, which are: the search spaces for W/L are feasible values for the given
IC technology; the bias conditions of all transistors are guaranteed, and the computing
time required by evolutionary algorithms is diminished because the convergence of the
algorithms being improved.
Finally, real IC designs not only require accomplishing industrial target specifications,
but also they should do it plus guaranteeing robustness, which means the designed IC
must support Process, Voltages and Temperature (PVT) variations. This is directly
related to yield improvement, i.e. guaranteeing the correct work of a high percentage of
fabricated chips. In addition, another strategy to estimate the robustness with respect to
parameter variations, like performing sensitivity analysis, is also presented in this Thesis.
At the end, the main contribution of this Thesis is the introduction of a multi-objective
optimization approach for analog ICs by combining gm/ID technique and evolutionary
algorithms, and by including PVT variation analysis. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| dc.relation | citation:Sanabria-Borbon A.C. | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Optimización/Optimization | |
| dc.subject | info:eu-repo/classification/Circuitos analógicos/Analog circuits | |
| dc.subject | info:eu-repo/classification/Algoritmos evolutivos/Evolutionary algorithms | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.title | Optimization of analog integrated circuits including variations | |
| dc.type | info:eu-repo/semantics/masterThesis | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
