dc.contributorJUAN MANUEL RAMIREZ CORTES
dc.contributorJOSE DE JESUS RANGEL MAGDALENO
dc.creatorHECTOR DANIEL RICO ANILES
dc.date2014-09
dc.date.accessioned2023-07-25T16:21:05Z
dc.date.available2023-07-25T16:21:05Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/190
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7805412
dc.descriptionCompressed sensing is a recently proposed technique aiming to acquire a signal with sparse or compressible representation in some domain, using a number of samples under the limit established by the Nyquist theorem. The challenge is to recover the sensed signal solving an underdetermined linear system. Several techniques such as the l1 minimization, Greedy and combinatorial algorithms can be used for that purpose. Greedy algorithms have been found to be more suitable in hardware solutions, however they rely on efficient matrix inversion techniques in order to solve the underdetermined linear systems involved. In this work, a FPGA-based Greedy algorithm architecture with a Chebyshev-type method to solve matrix inversion problem is presented. The architecture was developed for Xilinx Virtex 4 XC4VSX25, Xilinx Spartan 6 XC6SLX45, Altera Cyclone IV EP4CGX150DF31C7 and Altera Cyclone II EP2C35F672C6 FPGAs. The described architecture represents a low-cost and generic solution, robust to changes in word length and signal size. Besides, a MATLAB Graphical User Interface is developed for compressed sensing theory exploration focused on matrix and transform test. MATLAB GUI uses the Compressed Sampling Matching Pursuit algorithm to recover the sensed signal; reconstruction can easily be extended to other compressed sensing algorithms.
dc.formatapplication/pdf
dc.languageeng
dc.publisherInstituto Nacional de Astrofísica, Óptica y Electrónica
dc.relationcitation:Rico-Aniles H.D.
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Campos programables/Field programmable gate arrays
dc.subjectinfo:eu-repo/classification/Reconstrucción de imágenes/Image reconstruction
dc.subjectinfo:eu-repo/classification/Muestreo de imágenes/Image sampling
dc.subjectinfo:eu-repo/classification/Reconstrucción de señal/Signal recostruction
dc.subjectinfo:eu-repo/classification/Métodos de muestreo/Sampling methods
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleFPGA-based compressed sensing reconstruction of sparse signals
dc.typeinfo:eu-repo/semantics/masterThesis
dc.typeinfo:eu-repo/semantics/acceptedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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