| dc.contributor | VICTOR HUGO CHAMPAC VILELA | |
| dc.contributor | Jaume Segura Garcia | |
| dc.creator | HECTOR LUIS VILLACORTA MINAYA | |
| dc.date | 2014-05 | |
| dc.date.accessioned | 2023-07-25T16:21:02Z | |
| dc.date.available | 2023-07-25T16:21:02Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/165 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7805387 | |
| dc.description | The aggressive scaling of CMOS process technology poses serious challenges on
the lifetime reliability of ICs due to the stringent operating conditions and the
increase of process parameter variations. Reliability has become an important
concern of semiconductor industry and should be improved with each scaled
technological node in order to enhance yield. From semiconductor perspective,
reliability is the ability of a device to perform its required function under stated
conditions for a specified period of time. A semiconductor device fails when the
response parameters from the device can no longer perform its intended function.
Device failure may occur at any moment of device's lifetime.
As technology scales down, the likelihood of manufacturing defects such as
open and bridge defects increases due to the growth rate of interconnections.
Some of these defects are hard to be detected by traditional test methods and
could result in test escapes posing reliability issues. In addition, soft errors have
emerged as an important reliability concerns in SRAM memories due to lower
node capacitance and more stringent operating conditions. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| dc.relation | citation:Villacorta-Minaya H.L. | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Circuitos integrados/Integrated circuits | |
| dc.subject | info:eu-repo/classification/Nanotecnología/Nanotechnology | |
| dc.subject | info:eu-repo/classification/Pruebas/Testing | |
| dc.subject | info:eu-repo/classification/Confiabilidad/Reliability | |
| dc.subject | info:eu-repo/classification/SRAM/SRAM | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.title | Reliability enhancement of nanometer-scale digital circuits | |
| dc.type | info:eu-repo/semantics/doctoralThesis | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
