| dc.contributor | LIBRADO ARTURO SARMIENTO REYES | |
| dc.creator | FRANCISCO JAVIER CASTRO GONZALEZ | |
| dc.date | 2015-02 | |
| dc.date.accessioned | 2023-07-25T16:20:53Z | |
| dc.date.available | 2023-07-25T16:20:53Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/105 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7805326 | |
| dc.description | In a near future, MOS technology is expected to share space in electronic design with emerging technologies.
One of these is single-electronics, which implies the generation of circuits employing MOS
and single-electron transistors (SET).
Integrating components of both technologies SET and MOSFET results in a hybrid circuit. The
benefits of combining them are multiples. For instance, the hybrid circuits provide nanoscale dimensions,
ultra-low power consumption and the Coulomb Blockade Oscillation phenomenon, all of which
are characteristics of the SET. By contrast, high gain and current drive, high speed and very mature
fabrication technology are all advantages of the MOSFET technology.
Although the benefits of combining MOSFET and SET devices in the same circuit are attractive,
there are challenges at every step in the design path. In particular, this thesis focuses on the simulation
stage where the main problem is the nature of the flow of the charge, being continuous for
CMOS-devices while for SET-devices the flow is discrete. Thus, the methods to solve the equations
from both mechanisms are of different natures.
The main problem discussed in this thesis is that of tackling the challenge of including electronic
nanodevices in the integrated circuit design flow. More specifically, incorporating the SET while employing
the electrical modeling standards of the MOS transistor is the central difficulty to be considered.
The main objective of this research is to develop the modeling methodology of hybrid circuit simulation
MOS-SET. Besides, we will pursue particular objectives such as the development of models for
the single-electron transistor at functional level, and the proposed methodology for hybrid simulation.
The models that have been developed are fully compatible with standard IC circuit simulation frameworks
such as HSPICE.
The models have been tested in a series of bench-mark circuits showing excellent results. The
straightforward incorporation of the models into the IC verification flow results in a reduction on the
simulation time with respect to a model suggested in the literature.
Finally, although this work focuses on the modeling of the single-electron transistor device, the
methodology proposed can be extended to other devices or systems where the observed/measured
data is known. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| dc.relation | citation:Castro-Gonzalez F.J. | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Modelado/Modelling | |
| dc.subject | info:eu-repo/classification/Simulación/Simulation | |
| dc.subject | info:eu-repo/classification/Transistores/Single electron transistor | |
| dc.subject | info:eu-repo/classification/Ajuste de curvas/Curve fitting | |
| dc.subject | info:eu-repo/classification/Nanoelectrónica/Nanoelectronics | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/330703 | |
| dc.subject | info:eu-repo/classification/cti/330703 | |
| dc.title | Development of a hybrid simulation methodology for circuits composed by MOS and SET transistors | |
| dc.type | info:eu-repo/semantics/doctoralThesis | |
| dc.audience | generalPublic | |
