| dc.creator | Zerbini, Carlos | |
| dc.creator | Finochietto, Jorge M. | |
| dc.date | 2011-08 | |
| dc.date | 2011 | |
| dc.date | 2021-09-21T22:29:29Z | |
| dc.date.accessioned | 2023-07-15T03:27:08Z | |
| dc.date.available | 2023-07-15T03:27:08Z | |
| dc.identifier | http://sedici.unlp.edu.ar/handle/10915/125333 | |
| dc.identifier | issn:1850-2806 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7465764 | |
| dc.description | As communication networks evolve towards 100 gigabits per second rates to address increasing demand of data trafic, network processing solutions must be revised and upgraded to support this need. Meanwhile, Field Programmable Gate Array (FPGA) technology is becoming a much more interesting platform were to integrate network processing capabilities and compete with current available solutions. In this paper, we argue that FPGAs can play a signi cant role in this area. To this end, a general discussion on the technology is first introduced to later focus on the speci c requirements to implement network processing architectures. Finally, based on our previous experience on building network devices on FPGAs, we discuss a case study to illustrate some of the main drivers to consider FPGA as an interesting solution for network processing. | |
| dc.description | Sociedad Argentina de Informática e Investigación Operativa | |
| dc.format | application/pdf | |
| dc.format | 260-271 | |
| dc.language | en | |
| dc.rights | http://creativecommons.org/licenses/by-nc-sa/4.0/ | |
| dc.rights | Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) | |
| dc.subject | Ciencias Informáticas | |
| dc.subject | Packet networks | |
| dc.subject | network processing | |
| dc.subject | Reconfigurable logic and FPGAs | |
| dc.title | Reconfigurable network processing: the FPGA case | |
| dc.type | Objeto de conferencia | |
| dc.type | Objeto de conferencia | |
