Desarrollo de modelos de fallas de de sistemas electrónicos utilizando redes bayesianas

dc.creatorRoca, José Luis
dc.date2011-09
dc.date2011
dc.date2021-07-13T12:23:57Z
dc.date.accessioned2023-07-15T02:25:08Z
dc.date.available2023-07-15T02:25:08Z
dc.identifierhttp://sedici.unlp.edu.ar/handle/10915/121529
dc.identifierisbn:978-950-34-0749-3
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7461876
dc.descriptionThe scope of the present work is focused in the use of Belief Bayesian Nets (BBN) in order to model complex electronic system failures with hardware and built-in software. The theory of Bayesian networks can be thought as a fusion of influence diagrams and Bayes Theorem. The present analysis emphasizes their use in replacement of the conventional Fault Tree Analysis (FTA). A later study of software necessary to implement their application completes the proposed objective.
dc.descriptionSección: Diseño de hardware FPGA
dc.descriptionCentro de Técnicas Analógico-Digitales
dc.formatapplication/pdf
dc.format63-68
dc.languagees
dc.rightshttp://creativecommons.org/licenses/by-nc-sa/4.0/
dc.rightsCreative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.subjectIngeniería
dc.subjectBelief Bayesian Nets (BBN)
dc.subjectFault Tree Analysis (FTA)
dc.subjectConditional Probability Table (CPT)
dc.subjectInfluence diagrams (IF)
dc.titleDesarrollo de modelos de fallas de de sistemas electrónicos utilizando redes bayesianas
dc.typeObjeto de conferencia
dc.typeObjeto de conferencia


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