dc.creatorLöhner, Rainald
dc.date2017-11
dc.date2017
dc.date2020-04-23T14:52:02Z
dc.date.accessioned2023-07-14T19:27:03Z
dc.date.available2023-07-14T19:27:03Z
dc.identifierhttp://sedici.unlp.edu.ar/handle/10915/94120
dc.identifierhttps://cimec.org.ar/ojs/index.php/mc/article/view/5230
dc.identifierissn:2591-3522
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7435352
dc.descriptionMany state of the art CFD codes that exhibit low computational intensity (flops per RAM access) "saturate" the memory bandwidth of modern chips after only a few cores, thus minimizing any benefits from going to a higher number of available cores. This bottleneck is expected to become even more pronounced for future manycore systems. This has led to the quest for CFD solvers with minimal memory access. We report on recent developments and results for Finite Difference and Edge-Based Finite Element solvers. The best of these implementations yield one residual for only 6 fetches and 4 stores, regardless of the size of the stencil (and therefore the discretization order). This means that in terms of memory access they are competitive even with finite difference stencils as low as 2 (typical of CFD codes with 2nd order spatial discretization of fluxes and 4th order damping). Timings for a low Mach number finite difference code using a 6th order spatial discretization show competitive timings as compared to conventional loops. This bodes well for future HPC architectures.
dc.descriptionPublicado en: <i>Mecánica Computacional</i> vol. XXXV, no. 1.
dc.descriptionFacultad de Ingeniería
dc.formatapplication/pdf
dc.format9
dc.languageen
dc.rightshttp://creativecommons.org/licenses/by-nc-sa/4.0/
dc.rightsCreative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.subjectIngeniería
dc.subjectCFD codes
dc.subjectMemory bandwidth
dc.titleCFD Solvers with Minimal Memory Access
dc.typeObjeto de conferencia
dc.typeResumen


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