dc.creatorSanchez, Luis
dc.creatorPatiño, Giancarlo
dc.creatorMurray, Victor
dc.creatorLyke, James
dc.date.accessioned2017-11-07T04:10:29Z
dc.date.available2017-11-07T04:10:29Z
dc.date.created2017-11-07T04:10:29Z
dc.date.issued2015-02-27
dc.identifierhttps://hdl.handle.net/20.500.12815/32
dc.identifierhttps://doi.org/10.1109/LASCAS.2015.7250480
dc.identifier2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)
dc.description.abstractWe present the first hardware implementation for a FPGA-based universal link for the transmission of different low-voltage differential signaling (LVDS) connections through a single LVDS connection between different devices. The main objective of this work is to reduce the number of wires in a network, for example in some satellites, with several groups of devices, to a single LVDS connection. This paper proposes a new communication protocol for successfully coding and decoding the data sent through the single connection. We propose a solution for one of the difficulties of LVDS standard due to the amount of wires needed for a duplex connection, significantly reducing the amount of wires required for a large network. The proposed solution has been implemented in an Atlys board with a Spartan 6 FPGA showing promising results.
dc.languageeng
dc.publisherInstitute of Electrical and Electronics Engineers
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.rightsinfo:eu-repo/semantics/openAccess
dc.sourceRepositorio Institucional UTEC
dc.sourceUniversidad de Ingeniería y Tecnología - UTEC
dc.subjectProtocols
dc.subjectHardware
dc.subjectFrequency division multiplexing,
dc.subjectOptimization,
dc.subjectWires
dc.subjectField programmable gate arrays
dc.titleHardware implementation of a FPGA-based universal link for LVDS communications
dc.typeinfo:eu-repo/semantics/article


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