| dc.description.abstract | The advancement of microelectronics makes more and more portable electronic devices emerge in our daily lives. This brings a number of challenges to the semiconductor chain, from design, to the development of smaller and more efficient integrated circuits to encapsulation, since the components have become smaller, thinner, and with a larger number of input and output pins. These challenges are present in all chip fabrication processes and we can define molding as a critical process in particular. The transfer molding technology, which is consolidated and the main one used in this process, requires special care in the optimization of its parameters and materials, since there are more and shorter wires realizing the connection between the die and the substrate. The wire sweep, which is the entrainment of the wires due to the flow of the mold compound, becomes a problem, since losses in the molding process imply scrapping the component. The failure rate due to this type of failure can reach 2.5%, according to studies by major semiconductor chain manufacturers disclosed in (SANDGREN; ROTH, 2004). In this project the DRAM memory molding process with BOC BGA encapsulation type was simulated using the FSI module in COMSOL software. Results of wire sweep ratio obtained are within the average adding or subtracting one standard deviation and the maximum error rate ranging was 15.26% considering manufactured boards using the simulation parameters. | |
