Analysis of Mobility in Graded-Channel SOI Transistors aiming at Circuit Simulation

Abstract

This work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors us-ing an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-di-mensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjust-ing its parameters. This approach presents a percentage error smaller than 7.91% for low VDS.