Performance and Analysis of n-Type Vertically Stacked Nanowires Regarding Harmonic Distortion

dc.creatorCARVALHO, CESAR AUGUSTO BELCHIOR
dc.creatorSILVA, GENARO MARINIELLO DA
dc.creatorPAZ, BRUNA CARDOSO
dc.creatorBARRAUD, SYLVAIN
dc.creatorVINET, MAUD
dc.creatorFAYNOT, OLIVIER
dc.creatorMarcelo Antonio Pavanello
dc.date.accessioned2021-11-09T18:02:41Z
dc.date.accessioned2022-09-09T15:39:17Z
dc.date.accessioned2023-03-13T19:49:04Z
dc.date.available2021-11-09T18:02:41Z
dc.date.available2022-09-09T15:39:17Z
dc.date.available2023-03-13T19:49:04Z
dc.date.created2021-11-09T18:02:41Z
dc.date.created2022-09-09T15:39:17Z
dc.date.issued2020-08-11
dc.identifierCARVALHO, C. A. B.; MARINIELLO, G.; PAZ, B. C.; BARRAUD, S.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A. Performance and analysis of n-Type vertically stacked nanowires regarding harmonic distortion. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 15, p. 1-5, 2020.
dc.identifier1872-0234
dc.identifierhttp://148.201.128.228:8080/xmlui/handle/20.500.12032/6388
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/6160879
dc.description.abstractThispaperstudies theharmonic distortion (or non-linearity) of vertically stacked SOI nanowireswith differ-ent fin widths and channel lengths. The total harmonic distor-tion and third order harmonic distortion areused as figuresof meritin this work. The harmonicdistortion analysis is per-formed taking in consideration the differences between transis-tor’s intrinsic voltage gain and transconductance over drain current ratio.
dc.relationJICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)
dc.rightsAcesso Aberto
dc.subjectstacked nanowires
dc.subjectharmonic distortion
dc.subjectMOSFET
dc.subjectSOI transistor
dc.titlePerformance and Analysis of n-Type Vertically Stacked Nanowires Regarding Harmonic Distortion
dc.typeArtigo


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