Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

dc.creatorRangel-Patiño, Francisco E.
dc.date.accessioned2018-07-31T16:44:55Z
dc.date.accessioned2022-09-07T17:42:42Z
dc.date.accessioned2023-03-13T19:42:55Z
dc.date.available2018-07-31T16:44:55Z
dc.date.available2022-09-07T17:42:42Z
dc.date.available2023-03-13T19:42:55Z
dc.date.created2018-07-31T16:44:55Z
dc.date.created2022-09-07T17:42:42Z
dc.date.issued2018-07
dc.identifierRangel-Patiño, F. E. (2018). Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation. Tesis de doctorado, Doctorado en Ciencias de la Ingeniería. Tlaquepaque, Jalisco: ITESO.
dc.identifierhttp://148.201.128.228:8080/xmlui/handle/20.500.12032/1589
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/6159121
dc.languageeng
dc.publisherITESO
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf
dc.subjectEye Diagram
dc.subjectArtificial Neural Network
dc.subjectBroyden
dc.subjectPost-Silicon Validation
dc.subjectReceptor HSIO
dc.subjectKriging
dc.subjectSpace Mapping
dc.subjectSurrogate Models
dc.subjectSupport Vector Machines
dc.subjectSystem Margining
dc.subjectOptimization
dc.titleTransmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
dc.typeinfo:eu-repo/semantics/doctoralThesis


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