Improved Noise Immunity for Two-Sample PLL Applicable to Single-Phase PFCs

dc.creator	Lamo-Anuarbe, Paula (1)
dc.creator	Azcondo, Francisco J.
dc.creator	Pigazo, Alberto
dc.date.accessioned	2022-12-01T14:49:21Z
dc.date.accessioned	2023-03-07T19:39:40Z
dc.date.available	2022-12-01T14:49:21Z
dc.date.available	2023-03-07T19:39:40Z
dc.date.created	2022-12-01T14:49:21Z
dc.identifier	9781665436359
dc.identifier	https://reunir.unir.net/handle/123456789/13843
dc.identifier	https://doi.org/10.1109/COMPEL52922.2021.9645988
dc.identifier.uri	https://repositorioslatinoamericanos.uchile.cl/handle/2250/5908098
dc.description.abstract	Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling frequency used. Low signal-to-noise ratios (SNR) reduce the performance of the Two-Sample (2S) Phase Locked Loop (PLL). This effect can be compensated by including a smoothing filter action without increasing the overall complexity significantly. The resulting 2S with smoothing (2SS) is evaluated and validated by simulation and experimentally over a Totem Pole PFC.
dc.language	eng
dc.publisher	2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics, COMPEL 2021
dc.relation	https://ieeexplore.ieee.org/document/9645988
dc.rights	openAccess
dc.subject	noise immunity
dc.subject	PLL
dc.subject	synchronization
dc.subject	Scopus(2)
dc.title	Improved Noise Immunity for Two-Sample PLL Applicable to Single-Phase PFCs
dc.type	conferenceObject