Study of the utbbbe soi tunnel-fet working as a dual-technology transistor

dc.contributorUniversidade de São Paulo (USP)
dc.contributorUniversidade Estadual Paulista (UNESP)
dc.date.accessioned2022-04-28T19:44:05Z
dc.date.accessioned2022-12-20T01:23:01Z
dc.date.available2022-04-28T19:44:05Z
dc.date.available2022-12-20T01:23:01Z
dc.date.created2022-04-28T19:44:05Z
dc.date.issued2021-08-23
dc.identifierJournal of Integrated Circuits and Systems, v. 16, n. 2, 2021.
dc.identifier1872-0234
dc.identifier1807-1953
dc.identifierhttp://hdl.handle.net/11449/222332
dc.identifier10.29292/jics.v16i2.208
dc.identifier2-s2.0-85114042759
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/5402462
dc.description.abstract— In this work we further investigate the operation of theBESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the struc-ture, but also as an nMOS when a positive back bias is applied. The working principle is based on the generation of a channel of either holes or electrons by the back gate electric field, which can then be depleted through the front gate bias. TCAD device simulation was used for the proof of concept.
dc.languageeng
dc.relationJournal of Integrated Circuits and Systems
dc.sourceScopus
dc.subjectDual technology transistor
dc.subjectMOSFET
dc.subjectReconfigurable transistor
dc.subjectSilicon-On-Insulator (SOI)
dc.subjectTunnel-FET
dc.titleStudy of the utbbbe soi tunnel-fet working as a dual-technology transistor
dc.typeArtículos de revistas


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