| dc.contributor | Universidade de São Paulo (USP) | |
| dc.contributor | Universidade Estadual Paulista (Unesp) | |
| dc.date.accessioned | 2021-06-25T10:26:24Z | |
| dc.date.accessioned | 2022-12-19T22:12:52Z | |
| dc.date.available | 2021-06-25T10:26:24Z | |
| dc.date.available | 2022-12-19T22:12:52Z | |
| dc.date.created | 2021-06-25T10:26:24Z | |
| dc.date.issued | 2020-09-01 | |
| dc.identifier | 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. | |
| dc.identifier | http://hdl.handle.net/11449/206091 | |
| dc.identifier | 10.1109/EUROSOI-ULIS49407.2020.9365305 | |
| dc.identifier | 2-s2.0-85102968209 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/5386688 | |
| dc.description.abstract | In this paper we optimize the Dual-Technology Back-Enhanced SOI (DT BESOI) FETs varying the thickness of gate oxide, silicon film and buried oxide focusing on transfer characteristics. The DT BESOI optimization takes into account its behavior as both nMOS and pTunnel-FET device, which are obtained through the variation of positive and negative back biases. In the studied range, the optimized results were tox=lnm, tsi = 10nm and tBOX = 20nm. These DT BESOI results are compared with the conventional nMOS and pTFET devices. | |
| dc.language | eng | |
| dc.relation | 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020 | |
| dc.source | Scopus | |
| dc.subject | Dual-Technology (DT) | |
| dc.subject | Silicon-On-Insulator (SOI) | |
| dc.subject | Tunnel Field Effect Transistor (TFET) | |
| dc.subject | Ultra-Thin Body and Buried oxide (UTBB) | |
| dc.title | Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor | |
| dc.type | Actas de congresos | |
