Application of UTBBBE SOI tunnel-FET as a dual-technology transistor

dc.contributorUniversidade de São Paulo (USP)
dc.contributorUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2020-12-12T01:09:52Z
dc.date.accessioned2022-12-19T20:39:45Z
dc.date.available2020-12-12T01:09:52Z
dc.date.available2022-12-19T20:39:45Z
dc.date.created2020-12-12T01:09:52Z
dc.date.issued2019-08-01
dc.identifierSBMicro 2019 - 34th Symposium on Microelectronics Technology and Devices.
dc.identifierhttp://hdl.handle.net/11449/198329
dc.identifier10.1109/SBMicro.2019.8919316
dc.identifier2-s2.0-85077182307
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/5378963
dc.description.abstractIn this work we propose for the first time the use of the recently introduced UTBBBE SOI TFET (Ultra-Thin Body and Box Back Enhanced Silicon-On-Insulator Tunnel-FET) operating as a MOSFET device only by changing its bias condition. The principle is based on the carrier type generated by the back gate electric field. For negative back gate and drain biases applied in the device studied in this work, it works like a pTFET, while for positive ones it operates as an nMOS. TCAD device simulation was used for the proof of concept.
dc.languageeng
dc.relationSBMicro 2019 - 34th Symposium on Microelectronics Technology and Devices
dc.sourceScopus
dc.subjectdual technology transistor
dc.subjectMOSFET
dc.subjectReconfigurable transistor
dc.subjectSilicon-On-Insulator (SOI)
dc.subjectTunnel-FET
dc.titleApplication of UTBBBE SOI tunnel-FET as a dual-technology transistor
dc.typeActas de congresos


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