dc.contributorUniversidade de São Paulo (USP)
dc.contributorCI Brasil Program (CT-SP)
dc.contributorUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2019-10-06T15:39:35Z
dc.date.accessioned2022-12-19T18:32:15Z
dc.date.available2019-10-06T15:39:35Z
dc.date.available2022-12-19T18:32:15Z
dc.date.created2019-10-06T15:39:35Z
dc.date.issued2019-03-14
dc.identifier2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings, p. 21-24.
dc.identifierhttp://hdl.handle.net/11449/187543
dc.identifier10.1109/LASCAS.2019.8667587
dc.identifier2-s2.0-85064163027
dc.identifier0496909595465696
dc.identifier0000-0002-0886-7798
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/5368581
dc.description.abstractThis work analyzes the performance of measured Tunneling Field-Effect Transistors (TFET) when applied to analog circuits. The method uses a look-up table based behavioral model, taking the experimental results from a fabricated silicon pTFET as input. The Verilog-A behavioral language is used to implement the TFET model, enabling the use with spice-like simulators along with passive and active elements, achieving bigger circuits than other implementations involving numerical multiphysics simulation of the device. The model is further incremented with device capacitances, and the response of analog circuits is considered. An Operational Transconductance Amplifier (OTA) is presented, showing near 130 dB open-loop gain and 18.9nW power consumption.
dc.languageeng
dc.relation2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings
dc.rightsAcesso restrito
dc.sourceScopus
dc.subjectCircuit Simulation
dc.subjectTFET
dc.subjectVerilog-A
dc.titlePerformance evaluation of Tunnel-FET basic amplifier circuits
dc.typeActas de congresos


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