Brasil
| Actas de congresos
Efficient Realizations of CNOT gates in IBM's Quantum Computers
dc.contributor | Universidade Estadual Paulista (Unesp) | |
dc.contributor | Univ New Brunswick | |
dc.date.accessioned | 2019-10-04T12:38:15Z | |
dc.date.accessioned | 2022-12-19T18:10:37Z | |
dc.date.available | 2019-10-04T12:38:15Z | |
dc.date.available | 2022-12-19T18:10:37Z | |
dc.date.created | 2019-10-04T12:38:15Z | |
dc.date.issued | 2018-01-01 | |
dc.identifier | Proceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018). New York: Ieee, p. 58-62, 2018. | |
dc.identifier | http://hdl.handle.net/11449/185748 | |
dc.identifier | WOS:000469312100012 | |
dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/5366800 | |
dc.description.abstract | IBM's quantum computers implement gates from Clifford+T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison. | |
dc.language | eng | |
dc.publisher | Ieee | |
dc.relation | Proceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018) | |
dc.rights | Acesso aberto | |
dc.source | Web of Science | |
dc.title | Efficient Realizations of CNOT gates in IBM's Quantum Computers | |
dc.type | Actas de congresos |