| dc.creator | Hussein Ali, Mohammed | |
| dc.creator | Sherif, Noora H. | |
| dc.creator | Saady Abd-almuhsen, Ghufran Saady | |
| dc.date | 2019-07-30 | |
| dc.date.accessioned | 2022-11-05T02:18:44Z | |
| dc.date.available | 2022-11-05T02:18:44Z | |
| dc.identifier | https://produccioncientificaluz.org/index.php/opcion/article/view/29664 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/5140852 | |
| dc.description | The LMS algorithm is the most widely used in wireless applications such as equalization and adaptive filtering in imaging, communications, etc. The initialization of the LMS equalizer results from a pilot based channel estimation. This technique is achieved by using algorithms which adapt the parameters of Finite Impulse Response (FIR) equalizer to decrease the clutter and Inter symbol Interference (ISI) to give an accurate received signal. This paper presents the implementation of the LMS algorithm on Field Programmable Gate Arrays (F P G A). Construction of adaptive equa- lizer that is built on multiplier and adder is to achieve the Multiple Access Channel (MAC) process of the Finite Impulse Response (FIR). The parame- ters of the adaptive equalizer are modified off-hand by the LMS method based on insertion information’s. The proposed construction of this method designed using MatlabSimulink (R2015a) to treat with parallel constructer. The designed converted to VHDL coding pattern, as will as a VHDL test bench using Simulink HDL Coder tool to realize hardware directly from Simulink design. | es-ES |
| dc.format | application/pdf | |
| dc.language | spa | |
| dc.publisher | Universidad del Zulia | es-ES |
| dc.relation | https://produccioncientificaluz.org/index.php/opcion/article/view/29664/30493 | |
| dc.rights | Derechos de autor 2019 Opción | es-ES |
| dc.source | Opción; Vol. 35 Núm. 89 (2019); 611-625 | es-ES |
| dc.source | 2477-9385 | |
| dc.source | 1012-1587 | |
| dc.subject | Adaptive Equalizer | es-ES |
| dc.subject | Least Mean Square (LMS) algorithm | es-ES |
| dc.subject | field programmable gate array (FPGA) | es-ES |
| dc.subject | Finite Impulse Response (FIR) filter. | es-ES |
| dc.title | Optimum Design and Implementation of Adaptive Channel Equalization using HDL Coder | es-ES |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/publishedVersion | |
| dc.type | Artículo revisado por pares | es-ES |
