Diseño de una implementación eficiente en el área de latches pulsados para la técnica Boundary Scan Informe

dc.contributorM.Sc. Ing. Ronny García Ramírez
dc.creatorRetana-Corrales, Luis Felipe
dc.date.accessioned2019-03-15T21:15:44Z
dc.date.accessioned2022-10-19T23:01:52Z
dc.date.available2019-03-15T21:15:44Z
dc.date.available2022-10-19T23:01:52Z
dc.date.created2019-03-15T21:15:44Z
dc.date.issued2018
dc.identifierhttps://hdl.handle.net/2238/10422
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/4514587
dc.description.abstractThis document establishes a comparison between two di erent topologies for the IEE 1149.1 standard implementation. It is expected to give all the theoretical tools required to understand the design as well as to establish a comparison of each of the topological implementations in order to conclude which implementation is more e cient in terms of area consumption, energy consumption and speed.
dc.languagespa
dc.publisherInstituto Tecnológico de Costa Rica
dc.subjectFrecuencia
dc.subjectOperaciones
dc.subjectCeldas
dc.subjectCadenas
dc.subjectValidación
dc.subjectDiseño
dc.subjectFlip
dc.subjectIntegración
dc.subjectResearch Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electronics
dc.titleDiseño de una implementación eficiente en el área de latches pulsados para la técnica Boundary Scan Informe
dc.typelicentiateThesis


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