Diseño de un entorno mínimo de pruebas de validación de circuitos integrados en NI TestStand

Abstract

Circuits size reduction has been one of the most drastic changes over the years in circuit design and a handful of new problems along with; situation that is demanding circuit tests to be improved at an even faster pace. Circuit tests process consist on some stages and the one that has been most affected is the post-silicon validation, where a manufactured chip is verified, defining whether meets all the requirements for which it was designed for. Hence, validation environments are increasingly complex and need to be more flexible to improve circuit production. This work describes the process of establishing some preliminary foundations to create future post-silicon validation environments, based on a design methodology with an engineering process, which allows not only to create robust environments, but also to be custom made for circuits that are built at Integrated Circuits Design Laboratory at Electronics Engineering School.