Diseño de circuitos de columna para memoria SRAM para su integración en un microprocesador con arquitectura RISCV

Abstract

This document describes the design of the periphery circuits for 64 word of 32 bits SRAM memory, specifically for the write driver and sensing amplifier. Technology used was 180nm CMOS. All designs and simulations were deployed in Custom Compiler tool from Synopsys. Every circuit model considered on this work has been compared to each other, in order to determine which one suits better memory requirements. As comparison result, best option was chosen as per space and power consumption criteria has emerged and peripherals layout was designed to be included on memory layout design. Finally, SRAM memory with reading/writing capacity over all its positions, at 20 MHz clock and 1.8V power supply, was implemented.