| dc.creator | Villa, Francisco J. | |
| dc.creator | Acacio Sánchez, Manuel | |
| dc.creator | García Carrasco, José Manuel | |
| dc.date | 2006-04 | |
| dc.date | 2008-05-20T03:00:00Z | |
| dc.identifier | http://sedici.unlp.edu.ar/handle/10915/9512 | |
| dc.identifier | http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-1.pdf | |
| dc.identifier | issn:1666-6038 | |
| dc.description | Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics. | |
| dc.description | Facultad de Informática | |
| dc.format | application/pdf | |
| dc.format | 1-7 | |
| dc.language | en | |
| dc.relation | Journal of Computer Science & Technology | |
| dc.relation | vol. 6, no. 1 | |
| dc.rights | http://creativecommons.org/licenses/by-nc/3.0/ | |
| dc.rights | Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0) | |
| dc.subject | Ciencias Informáticas | |
| dc.title | Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures | |
| dc.type | Articulo | |
| dc.type | Articulo | |
