Desarrollo de encriptado AES en FPGA

dc.contributorBria, Oscar N.
dc.contributorVillagarcía Wanza, Horacio A.
dc.creatorLiberatori, Mónica Cristina
dc.date2006-02
dc.date2006
dc.date2008-04-18T03:00:00Z
dc.identifierhttp://sedici.unlp.edu.ar/handle/10915/4101
dc.identifierhttps://doi.org/10.35537/10915/4101
dc.identifierhttp://postgrado.info.unlp.edu.ar/Carreras/Magisters/Redes_de_Datos/Tesis/Liberatori.pdf
dc.descriptionThe Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. Synthesis results in the use of 460 logic cells and 4480 memory bits. The VHDL code was simulated using the test vectors provided in the AES submission package. The results are functionally correct. The architecture needs fewer logic cells than other ciphers and uses as few memory blocks as possible. The design goals were area and cost optimisation.
dc.descriptionFacultad de Informática
dc.formatapplication/pdf
dc.languagees
dc.rightshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.rightsCreative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.subjectCiencias Informáticas
dc.subjectRedes y Seguridad
dc.subjectInformática
dc.subjectAplicación informática
dc.subjectEncriptación de datos
dc.titleDesarrollo de encriptado AES en FPGA
dc.typeTesis
dc.typeTesis de maestria


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