bachelorThesis
Proposta de implementação paralela do classificador naive bayes em FPGA
Fecha
2021-08-31Registro en:
BARBOSA, Matheus Targino. Proposta de implementação paralela do classificador Naive Bayes em FPGA. 2021. 40f. Trabalho de Conclusão de Curso (Graduação em Engenharia de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2021.
Autor
Barbosa, Matheus Targino
Resumen
This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing speed and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gate Array (FPGA) is presented and evaluated regarding the hardware area occupation, processing time (throughput), and dynamic power consumption. Was implemented 5 designs with 64, 32, 16, 8 and 4 attributes for the inference step and 3 designs with 4, 8 and 16 attributes for the training step. In addition, a comparative analysis of the design was carried out with state-of-the-art works, showing that this implementation obtained more than $100\times$ speedup while reducing the area occupation and dynamic power.